Senior Power IC Design Engineer
Type (Full-time, part-time etc.): Full-time
Reports To: Design Engineering Manager
Silanna is a privately held semiconductor company with exciting new products for power conversion.
About the Role:
The Senior Power IC Design Engineer will be responsible for designing analog and mixed signal cells and at times leading the design of integrated POL, Multiphase and PMIC power management products. These products address the needs of consumer handheld, portable, server and telecom markets, and as such this candidate must have experience in the development of products intersecting one or several of these markets.
ESSENTIAL DUTIES & RESPONSIBLITIES:
- Participate in all aspects of the design cycle, including architecture development, transistor level design, layout supervision, lab debug and product characterization
- Research and development of state-of-the-art analog and mixed signal products for selected markets
- Developing IP including but not limited to Buck Regulators, Boost Regulators, LDOs, Bandgaps, Voltage and Current References, Clocks, Bias circuitry, etc.
- Process Selection, circuit design, system modeling, top level simulation, corner simulation, and design verification
- Provide guidelines to layout designers on circuit and full chip layout
- Author characterization and test plans for the IPs and Product.
- Support Test engineers on products you lead
- Support of new product release and FA
Education: BSEE Required; MSEE or PhD preferred.
Experience: 5+ years professional experience in analog and mixed signal IC design of power management Voltage Regulator IC products for POL, Multiphase and PMIC architectures serving Server, Telecom, Portable and Handheld Markets. Proven experience with high bandwidth error amplifier design and precision bandgap, and current balance/sensing design.
Core Competencies: Solid technical knowledge of semiconductor IC design including PMIC and POL voltage regulators.
Self-motivated, driven, and passionate individual with focus on results and meeting project schedules.
Strong knowledge of CMOS device physics and fabrication processes.
Strong knowledge of analog integrated circuit fundamentals.
Strong knowledge of parasitic and noise analysis skills.
Verilog/VHDL language and simulation verification experience is a plus
Mixed-signal simulation, interfacing with analog functions – Fluent with Cadence design environment.
Must possess strong written and verbal communication skills.