Senior Staff Digital Design & Verification Engineer

Type (Full-time, part-time etc.): Full-time

Reports To: Director of Design

Location: San Diego, CA

About Us:

As part of a small, fast-moving, innovation-focused company, the Senior Staff Digital Design & Verification Engineer will work closely with analog / mixed signal design engineers and systems applications engineers to define and design the digital section of our ICs. Digital plays a major role in all aspects of our ICs performance including system control, high speed processing of digitized data and parametric control of analog cells.

About the Role:

The Senior Staff Digital Design & Verification Engineer will have a variety of responsibilities that include:

• Design of digital (RTL) logic
• Working closely with Systems Applications and the Analog/Mixed signal Design team to ensure clear definition, proper functionality, high reliability and high yield
• Implementing the SCAN flow – DFT insertion, pattern generation and simulation
• Execution of the standard digital design flow tasks including clock distribution, power optimization, static timing analysis (STA), and logic synthesis
• Creating the scripts to support design and verification automation
• Completing comprehensive Digital Design Verification
• Development and support of UVM environments including self-checking UVM agents
• Generation of coverage reports
• Preparation of product support documents
• Creation of presentations and documents to support design reviews
• Estimation and management of tasks on schedule

About You:

QUALIFICATIONS AND EDUCATION REQUIREMENTS

• BSEE Required; MSEE preferred
• 10+ years professional experience in Digital Design and Verification
• Extensive experience using Verilog for RTL development.
• Comprehensive understanding of the full digital design flow include design, verification, linting, code coverage, synthesis, STA, and LEC
• Experience with System Verilog and UVM based verification..
• Experience with scripting languages such as perl, tcl, and Makefile
• Experience with source code management tools such as GIT
• Verilog-A, Verilog-ams is a plus
• Experience with place and route tools is a plus
• Working knowledge of IC development
• Must possess strong written and verbal communication skills
• Self-motivated, driven, and passionate individual with a focus on results